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I just received a board with jtec downloadable cable from my friend. But I can use this to download and test the program.
But during one of my experiment, I did something wrong (I think), some ports doesn't work for shift reg. but these ports are ok for combinational circuits input or output.
That's why I just want to know how to test all cpld function.
Well, for one thing it's "JTAG", not "jteg" or "jtec".
If you have a CPLD board and want to test it, you need to prope the pins on the chip or board. What board are you using?
If you don't have any extra hardware to do that, you can verify your design in something like ModelSim, which is free.
Added after 1 minutes:
You might be able to test it using the JTAG caple and some the CPLD vendors software. What software are you using?
CPLD is too complex to fully test yourself. The manufacturer uses an elaborate test fixture and test procedure.
JTAG allows you to configure the device, or read/write the state of individual pins. It would be pretty difficult to diagnose a chip malfunction that way, except for dead I/O pads. It may be easier to configure a counter or shift register that wiggles all the pins to make sure all the I/O pads are alive.
Please, stusy carefully next info about STAPL language.
You can use it for testing and even whole board through JTAG. Also, you can include a bitstream into JAM file to programm your device. I believe that will be useful for you.
Logically it seem like that, actually when I test by using simple gates (like or, and )the ports are working properly. But when I used like shift reg or FF there is no response at that port. When I switch to new cpld it work (that means my program is ok.)
Please, stusy carefully next info about STAPL language.
You can use it for testing and even whole board through JTAG. Also, you can include a bitstream into JAM file to programm your device. I believe that will be useful for you.
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