how to test 2GSPS 4bit flash adc

[ana192712]

i will design >1GSPS flash adc,but i do not konw how to convert 2GSPS digital code low speed digital code which logic analyzer can sample up to 500MHz.

 

[ricklin]

Use digital demux like LVDS receiver to make 4 serial data into 1 parallel data, so the same data bandwidth but 1/4 clock rate.

 

[ana192712]

ricklin
thanks,i learn this method from papers,for example,1GSPS digital output code is decimated by 16, which means 64MSPS digital output code rate. low speed digital code is analy by logic analyzer,then we can get dynamic parameters (SNR SFDR) through FFT analy.I confuse how we carry parallel data FFT. yon can detailed method???

 

[ricklin]

ricklin
thanks,i learn this method from papers,for example,1GSPS digital output code is decimated by 16, which means 64MSPS digital output code rate. low speed digital code is analy by logic analyzer,then we can get dynamic parameters (SNR SFDR) through FFT analy.I confuse how we carry parallel data FFT. yon can detailed method???

You need not to do parallel data FFT. After captured data on Logic analyzer, transfer it to PC and just write a simple program on PC (I use matlab for data analysis) you can turn the parallel data back to serial. Then you still carry a simple FFT.