How to take input in VHDL

[saur]

In C, we can take input from the user at runtime using the "scan" command.

Is there a way to do the same in VHDL i.e. without using a file with pre-defined values????

Thanks for any help and suggestions...

Saurabh

 

[barry]

VHDL IS NOT A SOFTWARE LANGUAGE, IT IS A HARDWARE LANGUAGE!!

What do you exactly mean by "take input"? VHDL is not designed to read a keyboard. VHDL is used to Describe Hardware (that's what the HD means).

 

[FvM]

You can read a file at runtime in a VHDL simulation. I you are talking about synthesized logic hardware, it has no native file handling capability by nature.

 

[TrickyDicky]

Std.textio does declare the text file INPUT, which should take input from the simulator console. But i have never used it, and i doubt many others gave either.

obviously, it is for simulation only. If you wanted it in and fpga you would have to included a keyboard driver, some methods of interrupting and a graphics output block. Sounds a bit like an embedded processor to me. Then you could use the scan C function on that