how to synthesize the don't care item

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For example I have some coding as below
How to use the design compiler to optimize this coding to make sure the minimum numbers of cells?
Actually this is a just example. If I replace the 'X' with '1', then this circuit will become the full adder. As a result, there is a only one cell mapping that is expected result.


Code VHDL - [expand]
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
------------------------------
ENTITY AA IS
PORT(XI:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
     XO:OUT STD_LOGIC(1 DOWNTO 0));
END AA;
------------------------------
ARCHITECTURE AA OF AA IS
BEGIN
 PROCESS(XI)
  BEGIN 
    CASE XI IS
WHEN"000"=>XO<="00";
WHEN"001"=>XO<="10";
WHEN"010"=>XO<="10";
WHEN"011"=>XO<="01";
WHEN"100"=>XO<="10";
WHEN"101"=>XO<="0X;
WHEN"110"=>XO<="0X";
WHEN"111"=>XO<="11";
    END CASE;
 END  PROCESS;
END AA;
 
Last edited by a moderator:

What are you exactly asking? A don't care specification will usually reflect a redundant part of the logic function. Hopefully the design compiler will utilize it to minimize resource usage or achieve other performance objectives, e.g. timing specifications.

A full adder will only fit into a single logic cell, if carry in and out are available for general connection. In recent FPGA, they typically connect to a dedicated carry chain.
 

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