How to synthesize the cores ??

[mhytr]

how to synthesize the cores generated by the core generator in ISE using synplify? I add the .edn file into the project in the synplify ,but it has no effect.

 

[eltonjohn]

EDN is already an EDIF file IT MEANS that is already SYNTHESIZED ..so you only need to ROUTE it to the final product that will implement it !

To do tho this it depends what is the ULTIMATE product enviroment you want to USE .XILINX ,,ALTERA ,, but certainly NOT SIMPLIFY !..simplify just PRODUCES an EDIF which you already have .,.Use ISE .. and import that EDN file to it !
then ROUT it .. and produce a PROGRAMMING file for the TARGET product !

 

[vkchau]

To use CoreGenerator from Xilinx for synthesis, you should add ".xco" file into your project.

 

[mhytr]

Thanks! But if i want to see how many LUTs a core takes,what can i do?

 

[vkchau]

You can read datasheet of those cores. Datasheet will give you how many LUTs will be used.

 

[baonguyenpro]

You can search on Xilinx_com.
Keyword: Name of the Core.

 

[baonguyenpro]

I use Core Generator to make Core
I can't simulate by Modelsim
Please show me.

 

[yasser_shoukry]

I use Core Generator to make Core
I can't simulate by Modelsim
Please show me.

The same happens with me