How to synthesize sfixed division.

[nandakishore.mehrwade]

Hi everyone,
I am using fixed_pkg.vhd for our project. I want to divide two signals of type sfixed. When I use normal division ('/') operand I am able to simulate. But when I try to synthesize, it shows error division operand cannot be synthesize. Can anyone please let me know how to proceed. Is there any package available to do this. Thank you in advance.

 

[TrickyDicky]

what problem are you getting? general refusal or timing failure?

I would never use the "/" operator directly because it offers no pipelining. For a decent clock speed, you will need several pipelining stages, which is probably why you are getting failures. Altera and Xilinx ofer fixed point divider IP blocks.