how to synthesize gated clock??

[JesseKing]

gated clock circuit

when synthesizing a circuit with gated clock, how to constrain it?

for example, a clock is gated as follows,
assign clk = ce? clkin : 1'b0;
in which clkin is the explicit input clock pin, gated by a 2-in and gate, and clk is fed to DFFs in the circuit.

how can i constrain this design?

if i creat_clock on clkin port and set_dont_touch_network, the "dont_touch" and gate can not drive the high fan-out, so large negative slack will appear.

who can tell me how to do

Best regards!

 

[lionchen]

creat_clock

clock is used to handle through CTS , whether it is gated clock or not

normally in DC, set_dont_touch_network will propagate the dont_touch attri throughout the net drived by the gate's pin. That is why u see large slack which is caused by the DRC violation.

u can set_ideal_network on clkin to mask the drc check of the clock net.

PS: the way u write gated clock is unsafe

 

[JesseKing]

gated clock

ok, i have solve the synthesis problem.
BTW, can u give me some advice on gated clock discription?

 

[lionchen]

gated clock. clock net

reg syn_clk_en;
always @(clkin or clk_en)
if (!clkin)
syn_clk_en <= clk_en;
assign clkout = clkin & (syn_clk_en | scan_en);

take care of the gating part when P&R
and the latch while CTS

 

[lijian_18]

gate clock circuit

In general, gate signal should be latch with neg-edge clock before AND with the gated-clock.

 

[cnspy]

set_dont_touch_network assign

Some synthesize tools can detect the gated clock and optimize it. Then do we need to write the gated clock circuit by ourself?

such as: power compiler, rtl compiler

 

[haosg]

gated clock synthesis rtl compiler

create_generated_clock clk -source clkin -divid 1

 

[jjww110]

gated clock logic circuit

let synthesis tool insert gate clock,add reasonable constrain

 

[power-twq]

synthesis gate clock

usually, we separate gated clock logic to a individual module,

and put this module next below the top module,

becuse the logic in gated clock module is simple generally,

you can hand instantiate them and check them carefully.

when synthesizing a circuit with gated clock, how to constrain it?

for example, a clock is gated as follows,
assign clk = ce? clkin : 1'b0;
in which clkin is the explicit input clock pin, gated by a 2-in and gate, and clk is fed to DFFs in the circuit.

how can i constrain this design?

if i creat_clock on clkin port and set_dont_touch_network, the "dont_touch" and gate can not drive the high fan-out, so large negative slack will appear.

who can tell me how to do

Best regards!