How to synchronize two LFSR between PRBS generator and checker

[stanford]

PRBS Generator -----> DUT -----> PRBS Checker

If we have the same LFSR with the same seed in the generator and the checker, at some point, the two LFSR will start generating the same sequence. We want to match the output from the generator to the checker through the DUT. since the DUT will have some latency, I don't know when we should start checking the two outputs. Is there a good way to synchronize the two LFSR or know when to start checking?

 

[dick_freebird]

If the two are identically constructed then although there
is latency, the latency ought to match "well enough" (if
you are not looking to push the speed to its limits, like
eye diagram testing of high speed serial links). But even
there, "golden unit" vs DUT with delay-matched chains
all the way from clock source to final comparison is the
only way I can see.

 

[stanford]

If the two are identically constructed then although there
is latency, the latency ought to match "well enough" (if
you are not looking to push the speed to its limits, like
eye diagram testing of high speed serial links). But even
there, "golden unit" vs DUT with delay-matched chains
all the way from clock source to final comparison is the
only way I can see.

Is there a way to make this work with arbitrary latency? Ideally, i want the checker to detect when it is synchronized and starts comparing.

 

[ThisIsNotSam]

you can certainly code something. I can think of so many workarounds. propagate a reset signal with the appropriate delay. if the LFSRs are built with primitive polynomials, you can very easily find out where you are in the sequence. some sort of queue mechanism could work well.

 

[stanford]

you can certainly code something. I can think of so many workarounds. propagate a reset signal with the appropriate delay. if the LFSRs are built with primitive polynomials, you can very easily find out where you are in the sequence. some sort of queue mechanism could work well.

i dont want to use a reset signal, that would not allow for arbitrary latency. this checker is in hw. I want a self checking hw that figures out when the two LFSR are synchronized and starts checking.

 

[ads-ee]

i dont want to use a reset signal, that would not allow for arbitrary latency. this checker is in hw. I want a self checking hw that figures out when the two LFSR are synchronized and starts checking.

assume the first value that you get is "correct" and load the lfsr with that value, all subsequent values should match, unless a) the initial value was wrong, b) the subsequent value is wrong. Regardless you'll already know you have an error. This method has the benefit of not requiring that you know the variable latency.

 

[ThisIsNotSam]

that works if the LFSR uses a primitive polynomial.

 

[FvM]

If the LFSR has Fibonacci topology, you can load the received bit stream to the shift register to initialize it to the same state.