How to synchronize multi-cycle signal in Clock domain Crossing ?

[sarang5s5]

We all know how to synchronize a pulse of a signal (single-cycle pulse) in Clock Domain Crossing (CDC) techniques. Can anyone help on how to synchronize a multi-cycle pulse ? For example, a single-bit signal goes HIGH for more than 1-clock cycle and goes LOW after some clock cycle. In this case, how to synchronize this signal to other clock doamin ?


Thanks in advance.

 

[FvM]

Depends on the intended behaviour with different clock frequency. Best you sketch what you expect.

 

[dpaul]

We all know how to synchronize a pulse of a signal (single-cycle pulse) in Clock Domain Crossing (CDC) techniques. Can anyone help on how to synchronize a multi-cycle pulse ? For example, a single-bit signal goes HIGH for more than 1-clock cycle and goes LOW after some clock cycle. In this case, how to synchronize this signal to other clock doamin ?


Thanks in advance.

@sarang5s5
For a single bit, not-so-frequently-changing signal, you can use the same technique!