How to synchronize module a and b of my Verilog code?

[SUNBELT]

Verilog guestion

I have to modules:

module a(......, output reg f,.....)

always @(posedge clock) begin
.....
.....
.....
if (.....)
f=1;
else if (....)
f=0;
end
endmodule

module b(...., input f,.....)
a call(....,.f(f),...);

always @(posedge clock) begin
I use f here end
endmodule
my problem is that the changes in f in "module a" appears one clock cycle later in "module b". I think f in "module a" changes after it is used in "module b". How can I synchronize them? Is there any way to solve this problem?

 

[barath_87]

Re: Verilog guestion

That is the inherent property of RTL .... or if you look at the the RTL schematic in your synthesis tool it will be in master slave configuration in this case...

I am open for corrections

Barath Ramesh.