How to synchronize between Digital and Analog macros in Mixed-signal IC layout?

[sicheng163]

Hi,all
Is there any have the experience of mixed-signal IC design?
I have a problem about the synchroniztion between digital part and analog macro.
we know, after CTS, there will be a delay between CLOCK source and DFFs' clk, and it's done automatically by APR tool such as Astro, but in the analog macro, clock buffer is inserted by the designer, how to synchronize them?
should I calculate an accurate delay in digital circuits and make the same delay in analog macro?
thanks!!!!

 

[rca]

the simpliest way is to have all flop in analog domain running on the opposite clock edge, to add by design a half clock cycle of marge.

 

[sicheng163]

the simpliest way is to have all flop in analog domain running on the opposite clock edge, to add by design a half clock cycle of marge.

I don't think that will make any sense since it becomes an asynchronous interface between Digital and Analog after CTS,
thanks anyway!

 

[dianin]

I think there is one way to synchronize digital with analog macro in Astro. You need to set analog clock port as sync pin and need to give insertion delay information (from analog port to flip-flop), once the tool knows this information tool will decide how much is required outside the analog macros to balance with digital flops and insert buffer accordingly. I do not remember the command but you can check the man page.

 

[rca]

I don't think that will make any sense since it becomes an asynchronous interface between Digital and Analog after CTS,
thanks anyway!

We currently used this opposite edges structure between digital/analog from 10 years with success, in 0.18um, 0.13um TSMC design.

 

[ebuddy]

I agree with rca. Using falling edge to handover from APR logic to macro is an easy and reliable way to hand off the data. We did it routely too.

We currently used this opposite edges structure between digital/analog from 10 years with success, in 0.18um, 0.13um TSMC design.