Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to sync fast domain clock to slow domain clock domain

Status
Not open for further replies.

luyuwang

Newbie level 1
Joined
May 26, 2009
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,289
synchronizing two clock domains

Hi,everyone:
now I design a FIFO,I have encounter this problem:
I use writer pointer and read pointer to determine full or empty status.
now I supose write clock is faster than read clock(maybe many times),before comparing the two pointers,I need synchronize write pointer to read pointer,the question is how to synchronizer fast domain clock to slow domain clock domain(write poniter to read pointer)?
thanks
handshake?or other method?
thanks again!
 

fast clock to slow clock

use clock divider circuit and give the divide clock signal to read
 

fast clock to slow clock signal sync

Maybe you can take slow clock as enable signal of fast clock, assume the two clock have the same phase
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top