How to switch your FPGA clock while system running

[Vonn]

iam trying to switch my clock while system running
I have used a MUX as a concurrent statment so that when power up If FPGA see 1 on an I/o pin it selects clock source 1 and if it see 0 it will select source 2 ...
it's a very simple code and working correctly ..
---------
entity switclock is
Port (c1,c2,mxcon : in std_logic ;
mxout : out std_logic
);
end switclock;

architecture Behavioral of switclock is
begin
mxout <= c1 when (mxcon='0')else c2;
end Behavioral;
-----------
so , where is the problem ?
the problem appears when you write the UCF file and assigned c1 to one of the dlls and c2 to another one ?
my questions is ?
1- Is there any problem in this MUX if the clock sources where the special DLLs ?
2- from where can you define the type of pad (BUF,BUFG,...etc)
I use ISE5.1 ...
Thanx

 

[dll_embed]

If you are using virtex II, have a try of BUFGMUX. It is designed to mux clocks. You may want to take a look at virtexII datasheet page 30.

regards

 

[Vonn]

unfortunately , Iam usig spartan II 200K

 

[brmadhukar]

Hi,
You can use IBUFG prior to DLL and use 1x output of the DLL as your clock so that UCF file does not give error
Madhukar

 

[hong_vito]

use dll