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What do you mean by that, can you explain a little, this way it is difficult to understand what you exactly want to achieve.
I need to support 4 timing modes.
10MHz
20MHz
33.33MHz
58.67MHz
66.66MHz
I need to support only 4 timing modes of the listed 5:
10MHz
20MHz
33.33MHz
58.67MHz
66.66MHz
By using a PLL/DCM.
Try multiplying your target frequencies by progressively increasing N. Do that for all the frequencies you are after until you hit a common VCO frequency (assuming PLL). I am skipping all sorts of stuff, but I'm going with the flow here and adhere to your posting style.
Also ...
I will conveniently (for me) take that to read:
Excellent! Take for example a source clock of 50 MHz and stuff that into a PLL. Multiply by 4, so you get a VCO frequency of 200 MHz.
Then divide that by 20, 10, 6, 3 for output frequencies of 10 MHz, 20 MHz, 33.33 MHz and 66.66 MHz respectively. And if you need 58.67MHz as well, I purposefully left that as an exercise for the reader.