# how to support different timing modes using a single, constant clock.

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#### hpb

##### Member level 2
here, i can use clock_enable signal to achieve the objective.

#### syedshan

What do you mean by that, can you explain a little, this way it is difficult to understand what you exactly want to achieve.

#### hpb

##### Member level 2
What do you mean by that, can you explain a little, this way it is difficult to understand what you exactly want to achieve.

I need to support 4 timing modes.
10MHz
20MHz
33.33MHz
58.67MHz
66.66MHz
BUT I should use a single reference clock.
I have one more signal clk_enable.
its instructed that varying the duty cycle of this signal i need to achieve the mentioned frequencies.

#### syedshan

Well I have read another of your post. Why dont you give some details and let us not assume...? It will help you brother more than it will help others to answer your question.

Well any ways, if you are using Xilinx FPGAs, then if you are using virtex 6 you can use clocking wizard by core generator and can generate the clocks of your desire from the MMCM, while if you are using Spartan or below virtex6 you can use DCM using same core generator software.

Look in Xilinx ISE software-> click on new file -> core generator -> clocking wizard(for V6) and there you go....

If you are using Altera, then I dont know but I think there must be some similar thing in quartus as well. Not sure of course since I have not used Altera.

Bests,
Shan

#### mrflibble

By using a PLL/DCM.

Try multiplying your target frequencies by progressively increasing N. Do that for all the frequencies you are after until you hit a common VCO frequency (assuming PLL). I am skipping all sorts of stuff, but I'm going with the flow here and adhere to your posting style.

Also ...

I need to support 4 timing modes.
10MHz
20MHz
33.33MHz
58.67MHz
66.66MHz

I will conveniently (for me) take that to read:

I need to support only 4 timing modes of the listed 5:
10MHz
20MHz
33.33MHz
58.67MHz
66.66MHz

Excellent! Take for example a source clock of 50 MHz and stuff that into a PLL. Multiply by 4, so you get a VCO frequency of 200 MHz.

Then divide that by 20, 10, 6, 3 for output frequencies of 10 MHz, 20 MHz, 33.33 MHz and 66.66 MHz respectively. And if you need 58.67MHz as well, I purposefully left that as an exercise for the reader.

hpb

### hpb

Points: 2

#### hpb

##### Member level 2
By using a PLL/DCM.

Try multiplying your target frequencies by progressively increasing N. Do that for all the frequencies you are after until you hit a common VCO frequency (assuming PLL). I am skipping all sorts of stuff, but I'm going with the flow here and adhere to your posting style.

Also ...

I will conveniently (for me) take that to read:

Excellent! Take for example a source clock of 50 MHz and stuff that into a PLL. Multiply by 4, so you get a VCO frequency of 200 MHz.

Then divide that by 20, 10, 6, 3 for output frequencies of 10 MHz, 20 MHz, 33.33 MHz and 66.66 MHz respectively. And if you need 58.67MHz as well, I purposefully left that as an exercise for the reader.