module counter
(
input clk, enable, rst_n,
output [31:0] count,
);
reg count=0;
output wire [7:0] Data_out_0;
output wire [7:0] Data_out_1;
output wire [7:0] Data_out_2;
output wire [7:0] Data_out_3;
assign Data_out_0 = count[7:0];
assign Data_out_1 = count[15:8];
assign Data_out_2 = count[23:16];
assign Data_out_3 = count[31:24];
always @ (posedge clk or negedge rst_n)
begin
if (~rst_n)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;
end
endmodule