how to stop a counter

[lalu]

hi frz,
yes i have stop the counter after one cycle of count that s it should not repeat the addresss.do u hve idea?

 

[Engineer_Bob]

just decode the counter output to produce a signal that’s active when you hit the maximum, and rig that signal to the reset, maybe “and” it with an actual reset to allow you start it running again. Just describe it in vhdl

Bob

 

[echo47]

Please explain more clearly what starts and stops your counter, and what you mean by not repeating the address.
Are you using VHDL, Verilog, schematic, or something else?

 

[kavitha_bonthu]

can you elobarate the question

 

[nxtech]

You want a single cycle counter? You want to do a modulo down counter. Start your count with whatever value you need then count down only one value.

E

 

[sameem_shabbir]

Use some signal e.g stp_cntr
assign it to value 0 when counter reaches the stop value

use stp_cntr as chip enable for counter

 

[lalu]

in my project, i need 2 store in 64 array register each with 8 bits.then i have to call one by one using counter. these bits are then processed(multiplication) and then again returned to the register.hw to do this in verilog?iam attaching the code what i tried for 4 bits.plz correct it.
module module1(in1,in2,in3,in4,out1,out2,out3,out4,clk,reset,add);
input [255:0]in1,in2,in3,in4;
output [3:0]out1,out2,out3,out4;
input clk,reset;
output [5:0]add;
reg [3:0] u_r [0:63];
reg [3:0] u_r1 [0:63];
reg [3:0] u_r2 [0:63];
reg [3:0] u_r3 [0:63];
always@(posedge clk)
begin
//integer i;
//for(i=0;i<=63;i=i+1)begin
// u_r=in1[((i*4)+3)i*4)]
// end
//end
u_r[0] = in1[3:0];
u_r[1] = in1[7:4];
u_r[2] = in1[11:8];
u_r[3] = in1[15:12];
u_r[4] = in1[19:16];
u_r[5] = in1[23:20];
u_r[6] = in1[27:24];
u_r[7] = in1[31:28];
u_r[8] = in1[35:32];
u_r[9] = in1[39:36];
u_r[10] = in1[43:40];
u_r[11] = in1[47:44];
u_r[12] = in1[51:48];
u_r[13] = in1[55:52];
u_r[14] = in1[59:56];
u_r[15] = in1[63:60];
u_r[16] = in1[67:64];
u_r[17] = in1[71:68];
u_r[18] = in1[75:72];
u_r[19] = in1[79:76];
u_r[20] = in1[83:80];
u_r[21] = in1[87:84];
u_r[22] = in1[91:88];
u_r[23] = in1[95:92];
u_r[24] = in1[99:96];
u_r[25] = in1[103:100];
u_r[26] = in1[107:104];
u_r[27] = in1[111:108];
u_r[28] = in1[115:112];
u_r[29] = in1[119:114];
u_r[30] = in1[123:120];
u_r[31] = in1[127:124];
u_r[32] = in1[131:128];
u_r[33] = in1[135:132];
u_r[34] = in1[139:136];
u_r[35] = in1[143:140];
u_r[36] = in1[147:144];
u_r[37] = in1[151:148];
u_r[38] = in1[155:152];
u_r[39] = in1[159:156];
u_r[40] = in1[163:160];
u_r[41] = in1[167:164];
u_r[42] = in1[171:168];
u_r[43] = in1[175:172];
u_r[44] = in1[179:176];
u_r[45] = in1[183:180];
u_r[46] = in1[187:184];
u_r[47] = in1[191:188];
u_r[48] = in1[195:192];
u_r[49] = in1[199:196];
u_r[50] = in1[203:200];
u_r[51] = in1[207:204];
u_r[52] = in1[211:208];
u_r[53] = in1[215:212];
u_r[54] = in1[219:216];
u_r[55] = in1[223:220];
u_r[56] = in1[227:224];
u_r[57] = in1[231:228];
u_r[58] = in1[235:232];
u_r[59] = in1[239:236];
u_r[60] = in1[243:240];
u_r[61] = in1[247:244];
u_r[62] = in1[251:248];
u_r[63] = in1[255:252];
end
always@(posedge clk)
begin
u_r1[0] = in2[3:0];
u_r1[1] = in2[7:4];
u_r1[2] = in2[11:8];
u_r1[3] = in2[15:12];
u_r1[4] = in2[19:16];
u_r1[5] = in2[23:20];
u_r1[6] = in2[27:24];
u_r1[7] = in2[31:28];
u_r1[8] = in2[35:32];
u_r1[9] = in2[39:36];
u_r1[10] = in2[43:40];
u_r1[11] = in2[47:44];
u_r1[12] = in2[51:48];
u_r1[13] = in2[55:52];
u_r1[14] = in2[59:56];
u_r1[15] = in2[63:60];
u_r1[16] = in2[67:64];
u_r1[17] = in2[71:68];
u_r1[18] = in2[75:72];
u_r1[19] = in2[79:76];
u_r1[20] = in2[83:80];
u_r1[21] = in2[87:84];
u_r1[22] = in2[91:88];
u_r1[23] = in2[95:92];
u_r1[24] = in2[99:96];
u_r1[25] = in2[103:100];
u_r1[26] = in2[107:104];
u_r1[27] = in2[111:108];
u_r1[28] = in2[115:112];
u_r1[29] = in2[119:114];
u_r1[30] = in2[123:120];
u_r1[31] = in2[127:124];
u_r1[32] = in2[131:128];
u_r1[33] = in2[135:132];
u_r1[34] = in2[139:136];
u_r1[35] = in2[143:140];
u_r1[36] = in2[147:144];
u_r1[37] = in2[151:148];
u_r1[38] = in2[155:152];
u_r1[39] = in2[159:156];
u_r1[40] = in2[163:160];
u_r1[41] = in2[167:164];
u_r1[42] = in2[171:168];
u_r1[43] = in2[175:172];
u_r1[44] = in2[179:176];
u_r1[45] = in2[183:180];
u_r1[46] = in2[187:184];
u_r1[47] = in2[191:188];
u_r1[48] = in2[195:192];
u_r1[49] = in2[199:196];
u_r1[50] = in2[203:200];
u_r1[51] = in2[207:204];
u_r1[52] = in2[211:208];
u_r1[53] = in2[215:212];
u_r1[54] = in2[219:216];
u_r1[55] = in2[223:220];
u_r1[56] = in2[227:224];
u_r1[57] = in2[231:228];
u_r1[58] = in2[235:232];
u_r1[59] = in2[239:236];
u_r1[60] = in2[243:240];
u_r1[61] = in2[247:244];
u_r1[62] = in2[251:248];
u_r1[63] = in2[255:252];
end
always@(posedge clk)
begin
u_r2[0] = in3[3:0];
u_r2[1] = in3[7:4];
u_r2[2] = in3[11:8];
u_r2[3] = in3[15:12];
u_r2[4] = in3[19:16];
u_r2[5] = in3[23:20];
u_r2[6] = in3[27:24];
u_r2[7] = in3[31:28];
u_r2[8] = in3[35:32];
u_r2[9] = in3[39:36];
u_r2[10] = in3[43:40];
u_r2[11] = in3[47:44];
u_r2[12] = in3[51:48];
u_r2[13] = in3[55:52];
u_r2[14] = in3[59:56];
u_r2[15] = in3[63:60];
u_r2[16] = in3[67:64];
u_r2[17] = in3[71:68];
u_r2[18] = in3[75:72];
u_r2[19] = in3[79:76];
u_r2[20] = in3[83:80];
u_r2[21] = in3[87:84];
u_r2[22] = in3[91:88];
u_r2[23] = in3[95:92];
u_r2[24] = in3[99:96];
u_r2[25] = in3[103:100];
u_r2[26] = in3[107:104];
u_r2[27] = in3[111:108];
u_r2[28] = in3[115:112];
u_r2[29] = in3[119:114];
u_r2[30] = in3[123:120];
u_r2[31] = in3[127:124];
u_r2[32] = in3[131:128];
u_r2[33] = in3[135:132];
u_r2[34] = in3[139:136];
u_r2[35] = in3[143:140];
u_r2[36] = in3[147:144];
u_r2[37] = in3[151:148];
u_r2[38] = in3[155:152];
u_r2[39] = in3[159:156];
u_r2[40] = in3[163:160];
u_r2[41] = in3[167:164];
u_r2[42] = in3[171:168];
u_r2[43] = in3[175:172];
u_r2[44] = in3[179:176];
u_r2[45] = in3[183:180];
u_r2[46] = in3[187:184];
u_r2[47] = in3[191:188];
u_r2[48] = in3[195:192];
u_r2[49] = in3[199:196];
u_r2[50] = in3[203:200];
u_r2[51] = in3[207:204];
u_r2[52] = in3[211:208];
u_r2[53] = in3[215:212];
u_r2[54] = in3[219:216];
u_r2[55] = in3[223:220];
u_r2[56] = in3[227:224];
u_r2[57] = in3[231:228];
u_r2[58] = in3[235:232];
u_r2[59] = in3[239:236];
u_r2[60] = in3[243:240];
u_r2[61] = in3[247:244];
u_r2[62] = in3[251:248];
u_r2[63] = in3[255:252];
end
always@(posedge clk)
begin
u_r3[0] = in4[3:0];
u_r3[1] = in4[7:4];
u_r3[2] = in4[11:8];
u_r3[3] = in4[15:12];
u_r3[4] = in4[19:16];
u_r3[5] = in4[23:20];
u_r3[6] = in4[27:24];
u_r3[7] = in4[31:28];
u_r3[8] = in4[35:32];
u_r3[9] = in4[39:36];
u_r3[10] = in4[43:40];
u_r3[11] = in4[47:44];
u_r3[12] = in4[51:48];
u_r3[13] = in4[55:52];
u_r3[14] = in4[59:56];
u_r3[15] = in4[63:60];
u_r3[16] = in4[67:64];
u_r3[17] = in4[71:68];
u_r3[18] = in4[75:72];
u_r3[19] = in4[79:76];
u_r3[20] = in4[83:80];
u_r3[21] = in4[87:84];
u_r3[22] = in4[91:88];
u_r3[23] = in4[95:92];
u_r3[24] = in4[99:96];
u_r3[25] = in4[103:100];
u_r3[26] = in4[107:104];
u_r3[27] = in4[111:108];
u_r3[28] = in4[115:112];
u_r3[29] = in4[119:114];
u_r3[30] = in4[123:120];
u_r3[31] = in4[127:124];
u_r3[32] = in4[131:128];
u_r3[33] = in4[135:132];
u_r3[34] = in4[139:136];
u_r3[35] = in4[143:140];
u_r3[36] = in4[147:144];
u_r3[37] = in4[151:148];
u_r3[38] = in4[155:152];
u_r3[39] = in4[159:156];
u_r3[40] = in4[163:160];
u_r3[41] = in4[167:164];
u_r3[42] = in4[171:168];
u_r3[43] = in4[175:172];
u_r3[44] = in4[179:176];
u_r3[45] = in4[183:180];
u_r3[46] = in4[187:184];
u_r3[47] = in4[191:188];
u_r3[48] = in4[195:192];
u_r3[49] = in4[199:196];
u_r3[50] = in4[203:200];
u_r3[51] = in4[207:204];
u_r3[52] = in4[211:208];
u_r3[53] = in4[215:212];
u_r3[54] = in4[219:216];
u_r3[55] = in4[223:220];
u_r3[56] = in4[227:224];
u_r3[57] = in4[231:228];
u_r3[58] = in4[235:232];
u_r3[59] = in4[239:236];
u_r3[60] = in4[243:240];
u_r3[61] = in4[247:244];
u_r3[62] = in4[251:248];
u_r3[63] = in4[255:252];
end
counter count1(clk,reset,add);
wire [1:0]u_rr,u_ri,u_r1r,u_r1i,u_r2r,u_r2i,u_r3r,u_r3i;
assign out4 = u_r3[add];
assign out3 = u_r2[add];
assign out2 = u_r1[add];
assign out1 = u_r[add];
assign u_rr = out1[1:0];
assign u_ri = out1[2:1];
assign u_r1r = out2[1:0];
assign u_r1i = out2[2:1];
assign u_r2r = out3[1:0];
assign u_r2i = out3[2:1];
assign u_r3r = out4[1:0];
assign u_r3i = out4[2:1];
wire [255:0]i1,i2,i3,i4;
wire [3:0] o1,o2,o3,o4;
wire [5:0]addr;
ROM rom1(i1,i2,i3,i4,o1,o2,o3,o4,clk,reset,addr);
wire [1:0]v_rr,v_ri,v_r1r,v_r1i,v_r2r,v_r2i,v_r3r,v_r3i;
wire [1:0]re0, im0, re1, im1,re2, im2, re3, im3,re4, im4, re5, im5,re6, im6, re7, im7;
assign v_rr = o1[1:0];
assign v_ri = o1[3:2];
assign v_r1r = o2[1:0];
assign v_r1i = o2[3:2];
assign v_r2r = o3[1:0];
assign v_r2i = o3[3:2];
assign v_r3r = o4[1:0];
assign v_r3i = o4[3:2];
radix2 rad1(u_rr,u_ri,v_rr,v_ri ,re0, im0, re1, im1, clock);
radix2 rad2(u_r1r,u_r1i,v_r1r,v_r1i, re2, im2, re3, im3, clock);
radix2 rad3(u_r2r,u_r2i,v_r2r,v_r2i, re4, im4, re5, im5, clock);
radix2 rad4(u_r3r,u_r3i,v_r3r,v_r3i, re6, im6, re7, im7, clock);
wire indx,enable;
wire [9:0] outt1,outt2,outt3,outt4,outt5,outt6,outt7,outt8;
twiddlerom twr1(index,enable,outt1,outt2,outt3,outt4,clk);
// wire [1:0] D_R1,D_C1;
// signed_complex multiplier1(re0,im0,outt1,outt2,D_R1,D_C1);
// //signed_complex multiplier2(re0,im0,outt1,outt2,D_R1,D_C1);
endmodule
module counter (C, ALOAD, Q);
input C, ALOAD;
output [5:0] Q;
integer i;
reg [5:0] tmp;
always @(posedge C)
begin
if (ALOAD)
tmp = 6'b000000;
else
tmp = tmp + 1'b1;
end
assign Q = tmp;
endmodule