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How to start designing a low jitter monolithic PLL in CMOS?

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urmiaboy

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pll design

hello all,

I must design a low jitter monolithic pll in cmos technology but I donot know how to start? please help me ..
 

khouly

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Re: pll design

frist u must get the specs of the PLL u want ot design
second try to get the design equation of the PLL on system level and simulate it in time and S domains "system level"
the matlab simulink is very good for this task

try to optimize the loop parameters to get best performance of the system .

third procede to the circuit level , see each block of the PLL how u will implement it

then simulate the PLL on circuit level ,
the PLL compnent are
PFD : phase frequency detector
CP : charge pump
lf : loop filter
VCO
and the divider

visit www.circuitsage.com
and try national they have a good simulator
and there is a good system level simulator CPPsim
 

sugar_luo2003

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pll design

As for low jitter, few suggestions for you
1)VCO itself shall have very small phase noise at out of the PLL loop bandwidth
2)The output of Charge Pump shall have very small ripple which require the good match on charge current and discharge current.
3)All bias for the circuit shall have very good PSRR
4)Please keep the Power as clean as possible, put decoupling capacitor for your power rail.
5)Avoid the noise signal to affect the bias signal as well
 

tucura

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pll design

Low jitter can be 'cycle-to-cycle' needed for clock generators and
'rms' for local oscillators in comm systems. For clock generator
a ring oscillator can be used as vco, using CML inverters to
reduce sensitivity to power supply noise. Careful design of the
PFD to reduce dead-time influence is also recomended.
For use as local oscillator a VCO build around an LC tank is
best. The higher the Q of the tank, the lower the rms jitter.
Typical Q for an integrated inductor is 4.
 

purefen

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Re: pll design

U can analyze the jitter by the phase noise. The ADS and SpectrRF can hlpe you fininshing these things. It can provide you the lower bound of the jitter of ur circuit, because it olny calculate the device noise not including other noise which from power, reference and substrate noise.
As the result, u should be careful about these items by yourself.
If you would like to reduce your jitter more, raise the order of the loop-filter is another solution.
FYI.
 

ptoo30

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Re: pll design

pll low jitter 1 to 3GHz
i donot know the frequency so my thinking is correct or not for you?
1 for cmos ic, use 2 inverters type osilator (in ADS you can find as saple)
i experienced to design colpitts type, unfortunately phase noise was huge because of Vdd and bulk noise
2 phase noiseepends on Hz/1V :: considering the fluctuation of C,L,MOSFETgm minimum Kv shall be designed
3 Vdd noise reduction mostly common mode noise reduction :: use voltage regulator only for VCO and put an inductor at Vdd line
4 at least 100um distance from huge noise generating MOSFET to avoid bulk noise at CMOS Epi wafer case
 

RC13

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Re: pll design

urmiaboy said:
hello all,

I must design a low jitter monolithic pll in cmos technology but I donot know how to start? please help me ..

could you pleased state your frequency range and how low your jitter? for what application?
 

jxzhang

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Re: pll design

if it is a sophisticated architecture, it needs to run MATLAB?
 

CDRCDR

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pll design

Try to use Matlab to do the system level simulation,LC tank VCO is good option to you
 

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