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How to start a design with a new cmos process technology

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hippoo

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Hi,

If you were asked to start a design with a new cmos process technology, e.g. 0.35um cmos technology from some other vendor, how are you going to extract the level 1 parameters in order for you to do the basic calculation? From my point of view, there are two methods.

a. Direct use the parameters value; e.g. for bsim3v3 with level 49, the nmos parameters are vth0 = 0.4, u0 = 380 & etc. You are going to use these parameters as your level 1 parameters?

b. Plot id vs vds for various vgs and w/l ratio. From the plots, calculate the transistor parameters based on level 1 formula?

Or you are having some other methods? Kindly advice. Thanks in advance.
 

ashish_chauhan

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refer to the following paper It will definitly help you out:
"BSIM3v3 Key Parameter Extractions for Efficient Circuit Designs."
by Jitkasame Ngarmnil & Wichai Sangnak.

From ICSE2000 Proceedings Nov.2000
 

hippoo

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thanks for your guidance. sorry to tell you that i do not have ieee account. could you attach the paper to this topic?

thanks in advance.
 

coolradar

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I prefer to follow the second method because it usually directly on target. Besides, Level 1 formula are not accurate for short channel device such as 0.35um process, why would you bother to use level 1 model for your design?

More important thing is that you should read design manual for that specific technology. Every technology have different features, such as different resistor/capacitor model, layout rules and etc.

[quote="hippoo"

If you were asked to start a design with a new cmos process technology, e.g. 0.35um cmos technology from some other vendor, how are you going to extract the level 1 parameters in order for you to do the basic calculation? From my point of view, there are two methods.

a. Direct use the parameters value; e.g. for bsim3v3 with level 49, the nmos parameters are vth0 = 0.4, u0 = 380 & etc. You are going to use these parameters as your level 1 parameters?

b. Plot id vs vds for various vgs and w/l ratio. From the plots, calculate the transistor parameters based on level 1 formula?

Or you are having some other methods? Kindly advice. Thanks in advance.[/quote]
 

Blackuni

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Hi,

I recommend gm/Id based methodology. where plot of MOS transconductance efficiency vs dimension r inversion coefficient is used as ref. for optimal device dimns .

u can find many discussions related to this topic in forum. For any doubts/clarification let me know.

Thanks,
 

sutapanaki

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I would also recommend gm/Id methodology. At least this is what I'm using in my designs. When I go to a new technology I spend some time in the beginning to plot the curves, but then they become very handy.
 

wateror

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the appendix of allen's book gives some useful methods, you can refer to it
 

hippoo

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hi all,

i have found that my method "b. Plot id vs vds for variou........" works well, but it requires lots of cal.

the method mentioned by the journal also works well & requires less cal.

i would like to try the gm/Id method if i have free time. anyway, someone has tried these two methods b4 (journal & gm/Id)? which one leads to more precise results?

Blackuni & sutapanaki, could u brief me in detail how r u going to plot the graph according to the gm/Id method?

thanks.
 

sutapanaki

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The problem with method b) as I see it is that you try to measure parameters that you fit in a level 1 model. This model is not accurate for small L technologies. You use 0.35um which is already sensitive to short channel effects. In the paper you cited I noticed that the smallest L they are using is 0.5um. If you use 2-3 times bigger L than this for analog design, the square law model can still be ok. But it is not so if the technology is below 0.35mu.
gm/Id method takes as a central variable not Vdsat, but rather gm/Id (which gives you some idea about Vdsat because from square law model Vdsat=2/gm/Id). gm/Id also reflects the efficiency of the transistor i.e. how much gm you get for a given current - and it is primarily gm that you care about in analog design. Another ratio of importance in the method is gm/Cgs which is often called Ft, but also it is the price you pay - to get a certain gm you pay with capacitance which very often you don't want. A third ratio is gm/gds which is the intrinsic gain of the transistor. All those three variables are independent of W to 1st order, but depend on L.
In the gm/Id method one plots the current density Id/W as function of gm/id. Also gm/Cgs and gm/gds are plotted as functions of gm/id. These plots are usually enough to do design using them as sort of a look-up tables. Results are quite accurate, because you use what spice gives you, which is based on your models.
There is already a lot of literature on gm/id method, even here in the forum. But you can also look for the lectures of Boris Mourmann from Stanford university, or the online video lectures of prof. Boser from Berkeley (EE240). Also, as far as I know there is a book to be published soon dedicated to that method.
 

swolf

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I am working with 0.18 proccess, and I found that the method a) is good. I calculated out the Kn, Kp with the parameters in the model file, which are precise enough for hand cal.
 

luochuan

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for hand analysis, i think the method a) is enough!
we want to obtain the design relationships from hand analysis, not exact circuit parametres.
 

sutapanaki

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Well, I agree that for any technology one can find parameters that will be sort of ok. However, the circuits will be 20-30% off or more and then what's left is do the SPICE monkey business. Everyone has his/her own preferences for design, mine is definitely not playing with SPICE so much. I prefer the gm/Id approach because with it I'm almost right-on the first time, within 10% usually. Plus I can track pretty easy where the differences come from. Just an opinion.
 

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