how to solve this error?? anybody know?

[cloudz88]

vsim 3732 default binding

# Loading work.ram0(ram0_a)
# ** Error: (vsim-3732) assignment2a.vhd(78): No default binding for component at 'u2'.
# (Port 'dout' is not on the entity.)
# Region: /testbench/u1/u2
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/xilinxcorelib.blkmemdp_v6_3(behavioral)
# Error loading design



--------------------------------------------------------------------------------------------

my code

entity assignment2a is

Port ( Trigger : in std_logic;
Reset : in std_logic;
X : in std_logic_vector ( 9 downto 0 );
Romrdy : out std_logic;
output : out std_logic_vector ( 9 downto 0 );
n_clk : in std_logic;
m_clk : in std_logic
);

end assignment2a;

architecture Behavioral of assignment2a is


Signal Counter : std_logic_vector (3 downto 0);
Signal AddrA : std_logic_vector (9 downto 0);
Signal DinA : std_logic_vector (9 downto 0);
Signal WeA : std_logic;
Signal EnA : std_logic;
Signal AddrB : std_Logic_vector (9 downto 0);
Signal Dout : std_logic_vector (9 downto 0);

Component ram0 is
port (
AddrA : inout STD_LOGIC_VECTOR ( 9 downto 0 );
DinA : in STD_LOGIC_VECTOR ( 9 downto 0 );
WeA : in STD_LOGIC;
EnA : in STD_LOGIC;
ClkA : in STD_LOGIC;
AddrB : inout STD_LOGIC_VECTOR ( 9 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
ClkB : in STD_LOGIC
);

end Component;

begin

u2:component Ram0 Port Map ( AddrA=>AddrA,
AddrB=>AddrB,
DinA=>DinA,
WeA=>WeA,
EnA=>EnA,
ClkA=>m_clk,
Dout=>Dout,
ClkB=>n_clk
);

 

[shockie]

no bindin entity

I am not sure if you have to check these code:

"u2:component Ram0 Port Map ( AddrA=>AddrA, "
AddrB=>AddrB,
DinA=>DinA,
WeA=>WeA,
EnA=>EnA,
ClkA=>m_clk,
Dout=>Dout,
ClkB=>n_clk
);

 

[ship_baba]

no binding entity

hi

check your source file for dout