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how to solve the problem of inferred clock

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alekhyahetl

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hi....i am new to verilog,i wanted to know what is inferred clk??????...
i am getting warning like

( " Found inferred clock toplevel|clk with period 40.00ns. A user-defined clock should be declared on object "p:clk" )


can any one of you explain me about this.........
 

Dayn

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hi....i am new to verilog,i wanted to know what is inferred clk??????...
i am getting warning like

( " Found inferred clock toplevel|clk with period 40.00ns. A user-defined clock should be declared on object "p:clk" )


can any one of you explain me about this.........

I have the same error in VHDL design with Synplify Pro soft :

Found inferred clock top|clk with period 10.00ns. A user-defined clock should be declared on object "p:clk"

Did you fix your past error ?

Best Regards,

Dayn
 

alekhyahetl

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hi dayn.........

i didnt solve that problem...did u fix tht??????...if so please tell me
 

zel

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i think it is not a problem..it is just a warning.
and i think you design will be ok..its depends on how you design your design..
 

alekhyahetl

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ya....it is showing as a warning and there is no problem to the design,i wanted to know the reason, for that warning........can u explain me pls
 

alekhyahetl

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I have the same error in VHDL design with Synplify Pro soft :

Found inferred clock top|clk with period 10.00ns. A user-defined clock should be declared on object "p:clk"

Did you fix your past error ?

Best Regards,

Dayn

hi Dayn.....

During synthesis assign a timing constraint for specified inferred clock......u can rectify from this.
it is only defining the clock type(inferred,derived,declared and system).
 

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