how to solve setup and hold - step by step

[jitendravlsi]

Hi All,

Please tell me how to solve setup and hold step by step.

I mean to say that if setup is there then what should be our first step to solve this and if still it is not resolved then what should be our second step and so on?

In the same way for hold as well, what should be the steps?

THANX
JIT

 

[sunilbudumuru]

SETUP HOLD STEP BY STEP

Hello Jet,

Just go through the following board link


Regards,
Sunil Budumuru

 

[jitendravlsi]

Re: SETUP HOLD STEP BY STEP

Dear Sunil,

in the provided link it is there how to remove setup and hold violation.

but dear please tell me

if setup is there then which method we should implement first and still if we face setup violation then which method we should implement second and so on.

We know the options like 1) reduce freq 2) reduce comb delay 3) reduce clk-q delay 4) play with skew
but tell me which option i should try first

I dont know, but there would be a series of steps to follow to remove setup violation. Blindly we can't opt any one option to meet our requirement.

hope you got my question....


thanx
jit

 

[shanmugaveld]

SETUP HOLD STEP BY STEP

@jitendravlsi
For setup
say you have to meet the timing of 100Mhz.
if you provide the constraint more than 100Mhz then you can reduce the frequency.
else you can change options in your tool settings for maximum speed.
if it is not yet solved you can go for the reduction of combo delay.

 

[sunilbudumuru]

SETUP HOLD STEP BY STEP

there are different ways that we can follow to fix setup.

1) reduce freq
2) reduce comb delay
3) reduce clk-q delay
4) play with skew

(A)
if your design is not operating at the required frequency whats the use. it should be the last option. atleast one should not think of this option and try to fix (see below) setup violations even early stages of the design cycle.
(B)
"reduce comb delay" - one should think of this option first. but should not effect the functionality. logic restructuring, logic duplicating, critical path optimization techniques etc
(C)
"reduce clk-q delay" --- this is fixed for a specific library cell. we cannot change the delay of it. all we can do is to select another cell of same type from the lib that has eevn better timing characterstics to meet your timing. its simply upsizing/downsizing of the cells. just u play with it.

one can avail either of (B),(C) options.

(D) last comes, playing with skew. this is last cos, it might effect the hold time.

i dont consider "reduce freq" is a valid option to fix setup. ofcourse it will fix but at the cost of reducing the frequecy. not at all suggestable.

regards,
Sunil Budumuru

 

[jitendravlsi]

Re: SETUP HOLD STEP BY STEP

Thanks Sunil

so you mean our precedence should be:


1) reduce comb delay
2) reduce clk-q delay
3) play with skew
4) reduce freq

Now tell me one thing

suppose if we do this(reduce combo delay) optimization at post-route stage.

Then will it not disturb the already placed cells and result in congestion?

thanx
jit

 

[sunilbudumuru]

SETUP HOLD STEP BY STEP

try to reduce the combo delay at the prelayout STA itself. to avoid such logic optimization during CTS stage, we do prelayout STA.

So it is always considered to have a timing clean netlist for PNR stage.
So it is always considered to have a timing clean netlist for PNR stage.
So it is always considered to have a timing clean netlist for PNR stage.

anyway , "routing, resizing cells " will be done duing the pre/post CTS for fine tuning of performance of the design.

Regards,
SunilB