sarmad88
Junior Member level 2
hi anyone
in my project when exchange this statements:
with ir(3 downto 1) select
output<=mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result when "000",
variance_result when "001",
st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result when "010",
rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result when "011",
covariance_result when "100",
mse_result when "101",
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when others;
by :
process(ir,mean_result,variance_result,st_dev_result,rms_result,covariance_result,mse_result)
begin
case ir(3 downto 1) is
when "000" =>output<=mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result (16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result (16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result;
when "001" =>output<=variance_result;
when "010" =>output<=st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result;
when "011" =>output<=rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result;
when "100" =>output<=covariance_result;
when "101" =>output<= mse_result;
when others=>null;
end case;
end process;
this warning produced:
WARNING:Xst:737 - Found 32-bit latch for signal <output>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
why? and how can remove this warning??
in my project when exchange this statements:
with ir(3 downto 1) select
output<=mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result when "000",
variance_result when "001",
st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result when "010",
rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result when "011",
covariance_result when "100",
mse_result when "101",
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when others;
by :
process(ir,mean_result,variance_result,st_dev_result,rms_result,covariance_result,mse_result)
begin
case ir(3 downto 1) is
when "000" =>output<=mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result (16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result (16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result;
when "001" =>output<=variance_result;
when "010" =>output<=st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result;
when "011" =>output<=rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result;
when "100" =>output<=covariance_result;
when "101" =>output<= mse_result;
when others=>null;
end case;
end process;
this warning produced:
WARNING:Xst:737 - Found 32-bit latch for signal <output>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
why? and how can remove this warning??