Hello All,
I wanted to know what all are the options I have when I have to fix set up violation in a design ( with no hold time violation ) without changing anything in rtl.
What are the stratagies I can use ( not the tool stratagies of vivado )
Thanks
If you have enough Math background, please take a look at how Setup Slack was calculated.
Then, you can obviously make the Slack become positive by changing some factors in the equation.
For example, if I have this simple equation of Slack:
Slack = ( Tcycle + Tcapture_clock_path ) - ( Tlaunch_clock_path + Tdata_delay )
If Slack is negative, it means setup timing violation.
Then, Slack will be positive value if:
1/ Increasing Tcapture_clock_path
2/ Reducing Tdata_delay
3/ Reducing Tlaunch_clock_path
4/ Increase Tcycle, or slower the speed
In FPGA, mostly we need to make change on port/cell/buffer.. location.
It would give some effect to the delay.