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How to size transistors of this circuit

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Wanoz

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I have attached circuit and I am gonna run simulation. Before running simulation, transistors should be correctly sized to get the output.

I know how to size M5, M6 and M7 transistors in the figure, but the problem once having a voltage doubler (M1-M4 transistors). This voltage doubler affects all sizing and some design rules should be taken into consideration.
what kind of procedure that I can follow to size them.

without voltage doubler: M5=M7 and they have larger size ( e.g. 10500um/0.18um)

Normal voltage doubler: M1,M2=50u/0.18um

My question is that what ratios of M1/M5, M1/M6, M2/M5 and M2/M6 should be. 20171205_174707.jpg
 

erikl

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... what ratios of M1/M5, M1/M6, M2/M5 and M2/M6 should be.

They all lead the same current, so I think these ratios should be around unity, better 2 (even more for the PMOS), because there are 2 transistors in series.

You'd also need correspondingly huge clock drivers.
 

Wanoz

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You mean M5/M1<<2, M6/M1<2

Also, for voltage doubler, clock drivers (CLK, CLKB) should have large size, shouldn't they?

Wow, the design will have large area.
 

erikl

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You mean M5/M1<<2, M6/M1<2
For the same conductivity, PMOS(W/L)≈3*NMOS(W/L), depending on process, this factor 3 ≈ µn/µp .

If you generally would want the same conductivity (resp. losses) for the leading voltage doubler as for the trailing one, the transistors of the leading doubler should be as wide as those of the trailing doubler (not twice as wide as I said before, because there are 2 transistors in series at both doublers).

Hence M5/M1≈3 (because PMOS/NMOS) and M6/M1=1 (both NMOS).

Also, for voltage doubler, clock drivers (CLK, CLKB) should have large size, shouldn't they?
Yeah, as indicated before, but W/L about a factor of 10 lower for the last driving stage (depending on the required switching speed).

Wow, the design will have large area.
Right; but this depends on your required current, respectively on how much Rdson losses you will allow.
 
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    Wanoz

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Wanoz

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Large size voltage doubler means high power degradiation (i.e. low power conversion efficiency). I am aware of voltage doubler in the figure should have large size, but overall power efficiency is expected to be low.
 

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Is it possible to add a circuit between voltage doubler and the capacitor Cc? The design circuit should allow the capacitor charged from the voltage doubler meanwhile M5 is OFF. Once the transistor M5 is turned ON, the circuit should disengage the voltage doubler. The reason for designed circuit is to keep the voltage doubler on small size, so maintain high efficiency. What kind of circuit can be used?
 

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