Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to size the comparator latch?

Status
Not open for further replies.

vistapoint

Member level 5
Joined
Feb 20, 2005
Messages
91
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
2,125
Can anybody please tell me how to design this latch used in a comparator? How to size these transistors? Thanks
 

You need to connect the gates of TP5 and TP6 to the clock signal and the gates of TN5 and TN6 for the input signal(say v1 and v2, respectively). Also the gate of TN7 and TN8 go to clock.
As for the sizing, if you can want to compare v1 and v2, TN3~TN6 should have the same size. Also, you can change the size of these transistors to compare v1 with v2*N.
 

I know how to connect them, which is shown in the picture. so how to size them? how to bias them? according to specs? Please if anybody knows.

nxing said:
You need to connect the gates of TP5 and TP6 to the clock signal and the gates of TN5 and TN6 for the input signal(say v1 and v2, respectively). Also the gate of TN7 and TN8 go to clock.
As for the sizing, if you can want to compare v1 and v2, TN3~TN6 should have the same size. Also, you can change the size of these transistors to compare v1 with v2*N.
 

since it's a dynamic circuit, it don't need bias. Also, the size for Nmos depend on the comparation ratio of the input signal and the size of the pmos is depend on how fast you want to (dis)charge the nodes.
 

The answer is still too brief. I cannot click'helped me':)

So still how to size those NMOS and PMOS, exactly?

nxing said:
since it's a dynamic circuit, it don't need bias. Also, the size for Nmos depend on the comparation ratio of the input signal and the size of the pmos is depend on how fast you want to (dis)charge the nodes.
 

Start with all transistors with minimum size...
Then if you need more precision, you increase the size of the input transistors...If latch is not strong enough you increase size of latch.
Keep size ratios.
Beware of parasitic caps when size too large
 
Hi, vistapoint,

Did you find solution for this by any other sources? If yes, could you please upload that here?
Even I'm interested in knowing how to size these transistors.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top