vistapoint
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Can anybody please tell me how to design this latch used in a comparator? How to size these transistors? Thanks
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nxing said:You need to connect the gates of TP5 and TP6 to the clock signal and the gates of TN5 and TN6 for the input signal(say v1 and v2, respectively). Also the gate of TN7 and TN8 go to clock.
As for the sizing, if you can want to compare v1 and v2, TN3~TN6 should have the same size. Also, you can change the size of these transistors to compare v1 with v2*N.
nxing said:since it's a dynamic circuit, it don't need bias. Also, the size for Nmos depend on the comparation ratio of the input signal and the size of the pmos is depend on how fast you want to (dis)charge the nodes.