Hi
If you are using RC triggered (bigFet) MOS devices as the power cells and just diodes at the IO's then you should be able to simulate ESD with Spice/Spectre without adding additional models for snapback. The idea of this approach is that the bigfet MOS is shunting the current in MOS mode, not snapback.
However, you should verify the voltage levels at the different points in the design. For instance the pad voltage at the IO's can still reach high voltage levels, higher than the trigger voltage of output drivers due to resistivity of the busline or diodes for instance. This 'breakdown information' for the sensitive nodes can be used to optimize placement and sizing of the ESD devices. Look for technical publications from Freescale at the EOS/ESD sympoisum (Stockinger, Michael - Miller, James W.). These publications provide first clues in simulating this kind of protection concept. Beware that most of the actual ESD clamps are proprietary and patented and cannot be copied for commercial use!
If you want to rely on snapback based clamps then simulation with spice-based tools is not easy at all. Personally I would not trust anyone claiming predictability of ESD performance. Setting up a correct model for the snapback of BJT's is a research topic. If the foundry cannot provide models then the best approach would be to rely on the preferred foundry partner for ESD. The person/company that provided the ESD solutions for your process technology can probably help you with models, rules and review to increase the likelyhood of a pass-first-time. Some ESD providers have simulation tools optimized for foundry nodes.
Never trust an ESD provider that claims to reach your ESD specification without them knowing your circuit/IO!