How to simulate VHDL code that write an output to a screen?

[gawad]

VHDL Questions

1- how to simulate VHDL code that write an output to a screen?

2- what is the importance of that code and how it can be used practically?

 

[sa007jbond]

Re: VHDL Questions

> 1- how to simulate VHDL code that write an output to a screen?

- With VHDL simulator, Modelsim or some alike ...


> 2- what is the importance of that code

- for any code is importance to being simple

> and how it can be used practically?
- With software Altera Quartus, Xilinx ISE, Lattice ispLever .... you can compile it and simple download to chips.

 

[omara007]

Re: VHDL Questions

1- how to simulate VHDL code that write an output to a screen?

It can't print the output to the screen (as far as I know) .. but if you use ModelSim for example, the command window may give you some outputs .. Yet, VHDL is not made to be like C/C++ .. you better get your results in the form of Waveforms, or dump files.

2- what is the importance of that code and how it can be used practically?

The importance is simply Design a system that is to be later manufactored to an ASIC IC .. or use to configure an FPGA ..
HDL is mainly used to describe Hardware Circuits as u can guess from its NAME .. it can also be used to verify designs thru testbenches ..
VHDL in general can't be used for generating stand-alone software like C/C++ ..
Hardware Designers most likely take the VHDL (or verilog) to a synthesis tool to convert the code into real logic citcuits ..
these are the basic uses of VHDL ..

 

[Sparc]

Re: VHDL Questions

1- how to simulate VHDL code that write an output to a screen?

>declare a line variable
variable my_line : line; -- type 'line' comes from textio
begin
write(my_line, string'("Hello World"));
writeline(output, my_line); -- write to "output"

> u can also use "report" statement with a valid severity.

2- what is the importance of that code and how it can be used practically?

>Importance of this code is only for small design simulations. For bigger designs, u will have to direct it from standard output to a file. So, that u can further dwell into the design to debug.

 

[zlop]

VHDL Questions

A TO Q1:
U need to write a hierachical testbench to view whether it is successful. It's complex.
A TO Q2:
It is a question of CODING STYLE. Also, it cannt be explained exactly here.