How to simulate VHDL AMS models using Cadence Spectre or AMS?

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chviswanadh

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Hello All,

Does anybody know how to simulate VHDL AMS models using cadence spectre or AMS.

I know We can simulate verilog A and verilog AMS models but not sure whether we can simulate VHDL AMS

Please give some inputs on this

Regards
Chviswanadh
 

Re: Simulating VHDL AMS

Yes you can simulate VHDL AMS in Cadence enviroment.

You have to create a symbol view for the VHDL AMS code...and bingo you can simulate it.

Regards
Sarfraz
 

Simulating VHDL AMS

first you create a sumbol ,and write vHDL ams code for it

then you can use spectre to simulate it
 

Simulating VHDL AMS

Refer to Cadence AMS designer. Only with this Cadence's tool u can simulate VHDL-AMS and Verilog-AMS blocks. It's better to study Verilog-AMS because it supports a connection modules (aka interface elements, IE) in nature. IE can automatically inserted between analog and digital domains. VHDL-AMS don't support rules for IE.
 

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