Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to simulate TIA in sp?

Status
Not open for further replies.
B

beabroad

Member level 4
Joined
Nov 24, 2003
Messages
76
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,288
Activity points
628
i am now designing a TIA in Cadence IC environment.

i know for LNA, i can use ports of 50ohm inner resistance for input and output ports, and use sp to simulate it.

however, for TIA, the input is current, and the port component output voltage only. so i want to know whether it is possible to simulate TIA using sp. thanks.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top