Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to simulate the offset voltage of the comparator??

Status
Not open for further replies.

leg1234

Member level 2
Joined
Dec 4, 2006
Messages
46
Helped
11
Reputation
22
Reaction score
3
Trophy points
1,288
Activity points
1,583
Hi, all

I am designing a latched comparator (dynamic type).
How can I set up the simulation to get the performance in offset and speed??
I also need Monte Carlo and Corner model verification. Thank you.

leg1234
 

luojiexiaojun

Junior Member level 2
Joined
Mar 14, 2008
Messages
21
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,378
i also need this help

look forward to your help
 

icehot

Newbie level 2
Joined
Apr 9, 2008
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,289
I think the Vos of the comparator will not appear correctly until you draw the layout and finish the post-simulation.
 

finfoun

Junior Member level 2
Joined
Apr 15, 2007
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,402
use Monte Carlo analysis need some variation parameter of your mosfet or resistor, for example tox, delta_L, delta_W and delta Vth
 

kumar123

Member level 3
Joined
Sep 5, 2006
Messages
57
Helped
9
Reputation
18
Reaction score
6
Trophy points
1,288
Activity points
1,639
Humungus said:
See my answer in post

Is this the same procedure even for folded cascoded Opamp structure ?
 

Humungus

Full Member level 6
Joined
Jul 10, 2001
Messages
384
Helped
41
Reputation
82
Reaction score
15
Trophy points
1,298
Activity points
3,985
kumar123,

The procedure I describe is for clocked (latched) comparator. In case of continuous time comparator, you need only perform a sweep of your input keeping the other one to a reference and then find the level at which your output toggle through a .DC analysis (this avoids errors due to the switching delay).
 

kumar123

Member level 3
Joined
Sep 5, 2006
Messages
57
Helped
9
Reputation
18
Reaction score
6
Trophy points
1,288
Activity points
1,639
Humungus said:
kumar123,

The procedure I describe is for clocked (latched) comparator. In case of continuous time comparator, you need only perform a sweep of your input keeping the other one to a reference and then find the level at which your output toggle through a .DC analysis (this avoids errors due to the switching delay).

Meaning as listed in Textbooks is it necessary to use dual power supply (Vdd=1.8 Vss=-1.8) and check the Vos for 0 Axis crossing of Sweep (say input) ?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top