how to simulate the influence of VTH difference on the

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foreverloves

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how to simulate the influence of VTH difference on the circuit

for example, in the circuit ,I want two MOS transistor to be exactly matched , but in fact, it won't after fabrication , how to simulate it under CADENCE ADE envirionment ?

urgent!!!

thank you!!!!!
 

Add a voltage source in series with the gate of one of the two transistors. Set the voltage to the Vth difference you want to simulate.
 

maybe use mente-carlo with change the parameter vth0 in spice model.
 

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