How to simulate offset in dynamic comparator

[gump38]

Hi,

Iam going to design a dynamic comparator for an Adc,

3 inputs, one for the input signal, one for the threshold voltage, and one clock
and 2 differentials outputs,
I would like to know how to simulate input offset in dynamic comparator

Can I use a ramp for the input signal in transcient simulation , but how to see input voltage

Thanks Guys

Gump

 

[dick_freebird]

Well, obviously you have to clock it, meaning a transient
analysis. An input ramp is one method. A looped binary
search, running an input offset variable, is another and
potentially more efficient (especially if you can skip DC
solution, and keep total simulation time short).

With an input ramp, your accuracy depends on the ramp
being slow, like more than 2^bits times the worst case
prop delay if you want "bits" worth of accuracy (and, to
get accurate, you probably need to "back-date" the
input value by the prop delay to see what-it-was at
input switchpoint, not output switchpoint.

A third, and ATE-test-solution realistic method is to put
the comparator inside an integrator / divider loop, let it
find its 50% duty cycle point on noise-driven-chatter,
and read the pre-divider voltage as a gained-up proxy
for the likely-unmeasurable Vio. Of course an internal
comparator could not be accessed in this way absent a
test mux tree. But the approach is valid to simulation.
Its total run time would probably fall between the previous
two methods (ramp will run full duration regardless of
where the comparator switches, so anywhere from 1%
to 99% of the run time would be wasted; search will
need only (bits) number of much shorter runs; integrator
time constant / settling will determine the run time you
need for accuracy(a box between settling tail, and
having a ripple residue > LSB on the integrator output).

 

[gump38]

Thanks for your reply Dick,
Iam going to use ATE test solution,

For the integrator, Iwill design an ideal Gm-C, how to choose the gain of th integrator ??

After equilibrium, is the input offset voltage is the difference between, the output of the integrator and the input voltage Vref,

Thanks in advance

 

[dick_freebird]

The Vio will be the input difference voltage (IN, VREF).
This difference on a modern low offset comparator will
challenge any PMU to measure. By driving the input with
a resistor-divided integrator output you pick up that
scale factor. You would prefer to put the REF input at
tester ground / common (offsetting suupplies if need be)
to maximize tester range/resolution limited performance.

In a simulation I'd just put VREF where it usually sits
and pick off the input difference with a VCVS, print the
final node voltage of that source output, badda-bing.

You might use a high gain vcvs, resistor in and capacitor
feedback, as a poor-boy integrator which you could fiddle
to explore any test sensitivities regarding integrator
qualities.