Thanks a lot!
I use DC to generate gated clock.
I heard latch is only used in gated clock in ASIC design. Is it right?
I think it must be gated clock cause the problem. I see the waveform.
And I found though data and clock change at the same time i.e at the
same delta time (I forbidden timing delay at global scope), clock
change is follow the data change.
As we all know data change must follow the clock change. So I guess
there must be gated clock cause some logic sequence chaos in
simulator.
Best regards,
Davy