I am trying to simulate a memristor crossbar array. But I found the sense margin is constant for 3x3 and 5x5. Theoretically, the sense margin should decrease with crossbar size.
In the graph, the result that the 1st readout is higher than the 2nd readout is as predicted by the theory.
I check the single device IV and it is the same like from the published paper.
Later I found out that the current on single device simulation is the same like the selected cell during the crossbar simulation. This is not correct.
It seems like the program fail to instantiate the devices.
I don't see question here, nor any material to support answering
one.
If you're getting current through something then it must have
been "instantiated" (inspecting the netlist would verify).
Not sure LTSpice is really your friend here, especially if you
are looking to process a veriloga model (LTSpice has its own
behavioral language, compatibility I suspect is less than total
(if any).