# How to simulate leakage power using Synopsys HSPICE

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#### pspfans

##### Newbie level 1
Hi, I have questions on how to simulate 65nm technology leakage current using HSPICE C-2009.03-SP1, and the model from foundary is BSIM4 V4.5 LEVEL54.

As we know, subthreshold leakage, gate tunneling leakage and junction tunneling leakage are the three main parts in DSM technologies. In our job, we need to get results of subthreshold leakage, gate tunneling leakage and junction tunneling leakage respectively. Gate tunneling leakage is easy to get, because HSPICE provides the templates such as LX71 for LEVEL 54 model, however, it does not provide them for subthreshold and junction leakage. So how shall we get subthreshold leakage and junction tunneling leakage(including trap-assistant-tunneling & band-to-band-tunneling). Take a NMOS transistor for example, if we drive its gate, source and bulk to 0V, and drive its drain to 1.2V, the traditional method of measuring drain current may contain some other current factors besides subthreshold leakage, so the result is not very exact. How shall we simulate the other two?

#### shandabogo

##### Newbie level 5

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