Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to simulate leakage of CMOS switch

Status
Not open for further replies.

taofeng

Advanced Member level 4
Joined
Mar 21, 2006
Messages
104
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
2,021
an interview question

what is the difference of these two inverters ? one of them I know is current starved inverter, the other I do not know the name.
 

Colbhaidh

Full Member level 6
Joined
Aug 10, 2004
Messages
395
Helped
141
Reputation
280
Reaction score
98
Trophy points
1,308
Location
Scotland
Activity points
3,756
Re: an interview question

They are both tri-tate invertors, output is high impedance when n and p turned off.
The Left hand side invertor could be used in current starved mode also.
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
7,236
Helped
2,117
Reputation
4,238
Reaction score
1,970
Trophy points
1,393
Location
USA
Activity points
58,016
an interview question

They are both current-starved. The difference is in the
position of the "master" (current mirror) and "switch"
elements.

The one on the right will probably have to embed an "on"
switch replica in the bias current master if you want a
particularly good match, while the one on the left is a
straight device match.

I think the one on the left will be "noisier" to the output
because the Miller kick from the input will directly perturb
the output node. The one on the right will be quieter at
the output, but may put more noise back into the bias
rack. You'd have to simulate with decent parasitic values
to judge properly.
 

xjy5216

Newbie level 3
Joined
Jun 14, 2009
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,272
an interview question

I think the left one would be slower than the right one becaouse of the miller effect.
 

viren_s

Junior Member level 2
Joined
May 25, 2006
Messages
24
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,283
Location
india
Activity points
1,462
Re: an interview question

Both will act as the invertor, with a combination of IN and vbp vbn.
so basically ithey differ in operation wise. for both they have different dependency on the IN vbp and vbn to the output.
Miller effect if it is it will be on both side, as you can not decide the input signal by just IN name. So miller effect will occur on both inverter.

Am i right??

regards
viren
 

walker5678

Full Member level 3
Joined
May 17, 2006
Messages
179
Helped
7
Reputation
14
Reaction score
3
Trophy points
1,298
Activity points
2,508
Re: an interview question

The left one can generate a very long trise or tfall by setting Vbp or Vbn to limit the current.

For the right one, if Vbp is very high or Vbn is very low, it will act the same as the left one, however, if Vbp is low enough or Vbn is high enough , it can generate a very short trise or tfall by using cascode structure to increase the gain of the inverter.

That's the difference, i think.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top