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How to simulate jitter in Hspice?

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kuohsi

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Jitter in SDM

Hi,
I simulate sigma delta in Hspice,
the SNR is only 60dB.
How do I simulate jitter in Hspice??
thanks!:D
 

Re: Jitter in SDM

Jitter will not contribute significant noise floor in such low SNR case.
In real chip (for audio application), jitter (tjc_c < 200ps) will degrade noise floor less than 6dB.
 

Re: Jitter in SDM

this situation is unrelated to jitter, because there isn't jitter created in transient simulation

the jitter noise power is PJ=A^2/2*(2*pi*fb*σt)^2/M, where σt is standard deviation of jitter assuming jitter has a Gaussian distribution with mean equal to zero
 

Re: Jitter in SDM

There's a nice section in "CMOS Mixed-Signal Circuit Design" by Jacob Baker that talks about how to simulate jitter with Spice. The method is to basically use the Single Frequency FM source (SFFM), then generate a squarewave clock from the zero-crossings of the SFFM.
You should take a look at the book for the full details.

Hope this helps
 

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