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How to simulate input offset of comparator after trimming?

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melkord

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Hi,
I need to simulate and show that the trimming circuit, i.e., 5bit current-output current-steering DAC, reduces the offset of a comparator.
But still confuse with the simulation setup.
I know how to simulate the input offset, but do not know how to simulate the comparator with the trimming circuit.
I am expecting something like this in the end:
1635843536869.png
 

arthorios

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The brute force way is to run all DAC settings for every Monte Carlo sample. Then for every sample, your trimmed offset is the one closest to the untrimmed mean.
 

arthorios

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How can I interrupt/pause Monte Carlo simulation?
You don't. Just run every DAC code for every sample. This means you will have 32 offsets for every sample. You would have to process this data afterward to get the expected plot you want.
 

melkord

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Just run every DAC code for every sample. This means you will have 32 offsets for every sample.
Hi, I wonder if you could explain a bit more in detail.
Sorry, I am really confuse with this setup.

What I do to get the offset is by sweeping the input voltage and then see at which value the output reaches 0.5VDD.
if I follow your plan, I would change the DAC settings in the Design Variables.
That means, for one DAC setting, I will get 500 MC runs.
In total, I would get 32*500 values of offset.

What should I do from here?
 

frankrose

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I guess you have a step size for offset trimming. So, you should pick from 32*500 offsets those values which are inside +-1 step, and check that the related DAC code is higher than 00000 and lower than 11111.
That means your trim range is enough, and 3 sigma of the trimmed offset is between -+1 DAC step, mean is 0.
 

arthorios

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For every MC run (single sample), you will have an offset. Now, in every MC run (again, single sample) you run all DAC settings, i.e., run your DC sweep for every DAC code. You will end up with 32 offsets for every MC sample (500 in your case). While processing the data, from the 32 offsets of every sample, you get the offset that is closest to the untrimmed mean. Ideally, if your trim is designed correctly, the trimmed offset will be around +/-1LSB of your offset DAC.
 

sutapanaki

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Running all DAC codes in every MC run is a waste of time. It is better if you create a veriloA script that does a binary search for the offset before trimming. Then run a binary search on the trim code as you observe where the comparator changes sign. Of course, in both cases the inputs of the comparator are shorted together to the common-mode voltage.
 

frankrose

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Running all DAC codes in every MC run is a waste of time. It is better if you create a veriloA script that does a binary search for the offset before trimming. Then run a binary search on the trim code as you observe where the comparator changes sign. Of course, in both cases the inputs of the comparator are shorted together to the common-mode voltage.
If he has a verilogA block to measure offset, trim comparator, measure trimmed offset again obviously it is easy, I guess it is not the case, but MC tran analysis of a comparator should be fast I think. Furthermore, can binary search work if comparator has some hysteresis? Maybe it can, I am not sure, and hysteresis is not mentioned but sometimes applied. And actually it is not mentioned that comparator is static or dynamic, clock controlled, last maybe can influence verilogA method. Not sure either.
 

sutapanaki

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Yes, of course, all these are valid questions and details to be tackled in the specific simulation case. I would, naturally, prefer to do this with a verilogA. It gives a lot of freedom in what can be simulated.
 

AMS012

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Doing MC with sweeping the DAC code from 0 all the way till 31 for every MC run is a pain. Instead, you can do a MC tran with the DAC code swept from low to high within the tran simulation with enough time gap between the code transition.
In this way, you can have a pseudo loop to break the run once the offset comes within your expected number. Remember, going on sweeping the DAC code allows you to hit the minimum offset for every run of MC. That's an overkill as, I believe, the purpose of the tuning DAC is to bring the offset down to within a certain number, and not necessarily hit the minimum. Post correction, anyway, there will be no 3-sigma business, which is also shown by your expected graph.
Hope this helps. Thanks.
 

melkord

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For every MC run (single sample), you will have an offset. Now, in every MC run (again, single sample) you run all DAC settings, i.e., run your DC sweep for every DAC code. You will end up with 32 offsets for every MC sample (500 in your case). While processing the data, from the 32 offsets of every sample, you get the offset that is closest to the untrimmed mean. Ideally, if your trim is designed correctly, the trimmed offset will be around +/-1LSB of your offset DAC.
Thank you!
I followed your method and get some result.
I wonder why I need to choose, out of 32 offsets, the offset that is closest to the untrimmed mean instead of the one that is closest to zero.
The picture below shows 3 samples of MC result after post-processing. each line consists of 32 offsets.
1635943852710.png
 

arthorios

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Thank you!
I followed your method and get some result.
I wonder why I need to choose, out of 32 offsets, the offset that is closest to the untrimmed mean instead of the one that is closest to zero.
The picture below shows 3 samples of MC result after post-processing. each line consists of 32 offsets.
View attachment 172687
Sorry for the confusion. This was in reference to the first figure plot you presented. Since in your get it's about offset, you get the ones closest to zero.
Regarding how to perform these sims, you can do it in an algorithmic way (as mentioned), which is how offset is usually trimmed post-fabrication. That's why I say this (what you did) is "brute force". But since you are running a simple DC sweep, even 10k runs wouldn't take much time.
 

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