how to simulate clock in verilog

[Sathish]

simulate clock in veriloig

hi all,
I want to simulate clock signal in verilog. Is that possible in simulation mode. If there is any possibility can any one give me the sample code for that.

with regards

 

[aji_vlsi]

simulate clock by verilog

hi all,
I want to simulate clock signal in verilog. Is that possible in simulation mode. If there is any possibility can any one give me the sample code for that.

with regards

Satish,
By simulating clock you mean a simple digital clock - with 50% duty cycle? If so:

  `timescale 1ns/1ns
  module clk_gen;
    reg clk = 0;
    always #10 clk = ~clk;
  endmodule

Now, if you are interested in Jitter etc. that's involved. Let us know.

HTH
Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 h**p://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar

 

[Sathish]

model clock in verilog

hi,
thanks for you suggestion. but can i simulate with combinational circuit?. i have attached the document with this message. pleae have a look at the attachment. i think that kind of simulation is not possible unless the propogation delay of the gate is specified in the code. note that my question is 'can we simulate such a circuit in verilog'.

thank you

with regards.