jmoore
Newbie level 3
Hi.
I have a ASIC design that I made staged mesh grid pattern on a mettle layer for ground on one mettle layer and now when I try and extract the design with full LRC parasitics it is to big to simulate. i.e. the caliber view alone is ~2G if the system can generate it. I have tried enabling reduced parasitics but it is auto disabled by caliber because L is enabled.
I would like to know how a power & ground "plane" (Large low impedance conductor on upper layer) is implemented in an analog IC and how do you go about simulating it.
Also are their auto stippling features that will generate a power plane with cutouts that will not bloat the extracted view to much? Currently my power plane generator p-cell makes 2x5 blocks spaced 2u apart in a staggered grid fashion (pretty much connected fill mettle).
software: Cadence Virtuoso, Caliber extraction
Design kit: TSMC65nm
I have a ASIC design that I made staged mesh grid pattern on a mettle layer for ground on one mettle layer and now when I try and extract the design with full LRC parasitics it is to big to simulate. i.e. the caliber view alone is ~2G if the system can generate it. I have tried enabling reduced parasitics but it is auto disabled by caliber because L is enabled.
I would like to know how a power & ground "plane" (Large low impedance conductor on upper layer) is implemented in an analog IC and how do you go about simulating it.
Also are their auto stippling features that will generate a power plane with cutouts that will not bloat the extracted view to much? Currently my power plane generator p-cell makes 2x5 blocks spaced 2u apart in a staggered grid fashion (pretty much connected fill mettle).
software: Cadence Virtuoso, Caliber extraction
Design kit: TSMC65nm