Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
You mean verilog simulation right? If so, then at the synthesis step where you generate the edf file, there should be an option to generate the equivalent verilog netlist too. After you get the netlist, compile it, along with the FPGA/ASIC library files. You can search this forum for post-synthesis simulation to get more info.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.