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How to simulate a EDIF schematic netlist?

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nbuzs

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I don't know if there is a tool could I use to simulate a EDIF file?

so how to add stimules? where to see waveforms?
 

skyfaye

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You mean verilog simulation right? If so, then at the synthesis step where you generate the edf file, there should be an option to generate the equivalent verilog netlist too. After you get the netlist, compile it, along with the FPGA/ASIC library files. You can search this forum for post-synthesis simulation to get more info.

- Hung
 

nbuzs

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Thanks!
You suggestion should be a way.
While I wonder if there is a way to simulate a EDIF netlist directly?
 

ljxpjpjljx

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why you want to do it ? the edif netlist is not used very commonly!
 

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