How to simulate a design in Verilog while test-bench in C++?

[jcpu]

an amateur qustion for help:

does anyone knows how do I sim
if I have my design in verilog
while test-bench in C++

 

[skyfaye]

Re: verilog & C++

If you're using VCS, then you can use the DirectC Interface.

From VCS Manual:

DirectC Interface — significantly improves ease-of-use and performance over existing PLI-based methods by allowing you to directly embed user-created C/C++ functions within your Verilog design description. VCS atomically recognizes C/C++ function calls and integrates them for simulation, thus eliminating the need to manually create PLI files. DirectC also eliminates the debugging and by bypassing PLI overhead, increases performance for simulating C/C++ code with Verilog. For details, see the VCS DirectC User Guide.

 

[ljxpjpjljx]

Re: verilog & C++

Usually in VCS and NCSIM , we all include the c/c++ lib through PLI method!

 

[jjww110]

verilog & C++

please use pli when use modelsim!!