Anbusivam
Newbie level 4
Hi all,
I have a situation in which one of our 65nm chip is driven by one another 45nm chip. We are having some glitch problems at the interface and I need to debug the same to understand the glitch source.
Now I've both the 45nm and 65nm process models and corresponding IO pad netlists. I am not sure how to do a simulation of these both together in a single simulation setup or in a single Hspice simulation deck.
Please help me in this.
Thanks,
Anbu
I have a situation in which one of our 65nm chip is driven by one another 45nm chip. We are having some glitch problems at the interface and I need to debug the same to understand the glitch source.
Now I've both the 45nm and 65nm process models and corresponding IO pad netlists. I am not sure how to do a simulation of these both together in a single simulation setup or in a single Hspice simulation deck.
Please help me in this.
Thanks,
Anbu