how to simulaate internal signals in ISE/modelsim ?

[buenos]

modelsim optimization

hi

how to simulaate internal signals in ISE/modelsim ?

now, i make extra ports for that, but when i want to try on the target, i have to remove the ports, resynth...

 

[Iptuous]

vish-4014

when you simulate the top level from ISE it just puts up the top level ports, but you can drag internal signals onto the waveform and rerun the simulation. if you want to keep that waveform with the internal signals for further use in the future, save it and run the simulation from within modelsim with the .fdo scriptfile rather than from ISE. otherwise ISE will regenerate the .fdo and the default waveform with only the port signals will come up.

 

[buenos]

modelsim startup.do

thanx

-how to drag internas signals?
-how to rerun the simulation?

could you answer in very basic level?
i dont know how to use the modelsim, i always just started simulation from ise.

 

[YenYu]

modelsim add wave no objects found

Hi,

Look at ur left hand side of ur screen, there is those signal in/out and internal signal, u can drag from there. Also there is those drop down list from there.

 

[echo47]

modelsim no objects found matching

I'm not sure what you mean by "how to simulate internal signals", because ModelSim simulates everything in your design. Maybe you meant "how to display signals in lower-level modules"? I do that by typing a command into the ModelSim Transcript window, or by putting the command into my ModelSim startup "do" script. For example, this command displays all the signals in my "filter" module:
add wave top/dsp/filter/*

If you want to exclude some of your HDL code during ISE XST synthesis, you can do this in Verilog:
// synthesis translate_off
... code ignored by XST ...
// synthesis translate_on

or this in VHDL:
-- synthesis translate_off
... code ignored by XST ...
-- synthesis translate_on

 

[buenos]

modelsim add wave internal signal vhdl

those things are not really the signals what i want.

can i edit the fdo somehow? how?

 

[echo47]

modelsim add module wave

Can you explain more clearly what you mean by "internal signals"?

What is an fdo? I don't see any fdo files in my ISE or ModelSim projects.

 

[buenos]

voptflow

when i wrote last time, i couldnt see your message, however you wrote 1 hour before.

yes: "how to display signals in lower-level modules"?"

add wave top/dsp/filter/*
what is top, dsp, filter?
for example, my top module is: top_testcard.vhd
the generated testbench iscican_toptest.vhw

this doesnt work:
add wave pcican_toptest/top_testcard/top_S4_CYC_O



i do post translate simulations because of the multiformat sources (v, vhd, ngc, edn), so the translate off doesnt help

add wave pcican_toptest/top_testcard/top_S4_CYC_O
# (vish-4014) No objects found matching 'pcican_toptest/top_testcard/top_S4_CYC_O'.
add wave top/pcican_toptest/top_testcard/top_S4_CYC_O
# (vish-4014) No objects found matching 'top/pcican_toptest/top_testcard/top_S4_CYC_O'.
add wave /pcican_toptest/top_testcard/top_S4_CYC_O
# (vish-4014) No objects found matching '/pcican_toptest/top_testcard/top_S4_CYC_O'.
add wave top_testcard/top_S4_CYC_O
# (vish-4014) No objects found matching 'top_testcard/top_S4_CYC_O'.

add wave pcican_toptest/top_testcard/top_S4_CYC_O/*
# (vish-4014) No objects found matching 'pcican_toptest/top_testcard/top_S4_CYC_O/*'.

add wave pcican_toptest/top_testcard/*
# (vish-4014) No objects found matching 'pcican_toptest/top_testcard/*'.

add wave uut/top_S4_CYC_O
# (vish-4014) No objects found matching 'uut/top_S4_CYC_O'.
add wave sim:/pcican_toptest/uut/the_pci_wbw_state/*
add wave /glbl/uut/top_testcard/top_S4_CYC_O
# (vish-4014) No objects found matching '/glbl/uut/top_testcard/top_S4_CYC_O'.
add wave /glbl/top_testcard/top_S4_CYC_Otop_testcard/top_S4_CYC_O
# (vish-4014) No objects found matching '/glbl/top_testcard/top_S4_CYC_Otop_testcard/top_S4_CYC_O'.
add wave /glbl/uut/top_S4_CYC_O
# (vish-4014) No objects found matching '/glbl/uut/top_S4_CYC_O'.
add wave /glbl/*/top_S4_CYC_O
# (vish-4014) No objects found matching '/glbl/*/top_S4_CYC_O'.
add wave /glbl/top_S4_CYC_O
# (vish-4014) No objects found matching '/glbl/top_S4_CYC_O'.

you can see, i have tried several ways

 

[echo47]

modelsim internal signals

My "top", "dsp", and "filter" are not file names. They are my Verilog module "instance names". (I don't know the equivalent VHDL terms, sorry. If you instantiate the same filter three times, and name them "filt1" "filt2" and "filt3", then those three names are what I mean by "instance names".) I can't guess your instance names without seeing your code.

My testbench instance name is "test", so either of these commands display all the signals in "test":
add wave *
add wave /test/*

My "test" module instantiates "top", so either of these commands displays all the signals in "top":
add wave top/*
add wave /test/top/*

My "top" module instantiates "dsp", so either of these commands displays all the signals in "dsp":
add wave top/dsp/*
add wave /test/top/dsp/*

My "dsp" module instantiates "filter", so either of these commands displays all the signals in "filter":
add wave top/dsp/filter/*
add wave /test/top/dsp/filter/*

I hope that makes sense!

 

[buenos]

simulating ngc file in modelsim

i dont really understand:
-signals in... (ports of module, or wire/signal inside?)


still doent work:
entity in teh automaticly generated vhw file: pcican_toptest its not instantiated anywhere, as i know.
top module entity: top_testcard, instantiated as UUT
submodule entity name: wbp, instantiated as the_intercon
one port of that: S2_CYC_O

so, this:
add wave /pcican_toptest/UUT/the_intercon/*
doesnt work.

Added after 9 minutes:

this work:
add wave UUT/*

but this doesnt:
add wave UUT/the_intercon/*

is it because of the post translate simulation?

its also good if i can check the signals/wires inside the topmodule.

 

[cheggy]

modelsim objetcs

Suggestion: go back to ISE Simulator, add testbench module, start simulation. From the list at Your bottom left side of screen drag & drop every signal You wish to watch (in/out/internal). Click on "Simulation" menu, then sub-menu "Restart". Finally, menu "Simulation", sub-menu "Run all" and then "Simulation", sub-menu "Stop". Now You should see waveform of every signal You've placed on screen.

 

[buenos]

how to see signal in ise

when i added the
add wave UUT/*
then i could see a huge amount of internal signals, but with useless names. maybe the synthezer renames internal signals...
but i cant recongnize which one is what i looking for.

synth is needed, because i can simulate only post translate, because of the mixed source file tipes.

 

[haytham]

ise simulator show internal signals

Hi
new versions of model sim make design optimization.
You need to pass the argument -novopt to your vsim command
either to change your script (if you have so) or to search in the simulation options in the tool about how to pass your options or command.do file to model sim

Regards
Haytham

 

[sawaak]

view internal signals with modelsim

Hi,
optimization can be off by setting the value of VoptFlow switch in modelsim.ini file to 0(default is 1),
find the following section in your modelsim.ini file(located in your modelsim folder)

[vsim]

; vopt flow
; Set to turn on automatic optimization of a design.
; Default is on
VoptFlow = 1

and change the VoptFlow = 0



thanks
sawaak

 

[echo47]

novopt fdo

Post-route simulation can be painful. It's basically an HDL representation of the routed chip. Your original design structure is gone. You may need to carefully study the post-route HDL code. You will probably find your HDL hierarchy flattened into one big module (unless you enabled keep_hierarchy during synthesis), plus some new modules containing Xilinx primitives. The HDL usually contains a large number of new signals, renamed signals, and deleted (optimized away) signals. Your top-level I/O signals should still exist.

UPDATE:

To display all the signals in your project:
add wave -recursive *