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How to shut down UCC28070A PFC controller?

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Advanced Member level 5
Jun 13, 2021
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The following document shows the UCC28070A PFC controller being disabled by a FET, Q2, which grounds the output of the UCC28070A’s current error amplifier (CAOA pin). It’s a transconductance error amplifier, but won’t grounding its output do damage to this error amplifier?

UCC28070A app note schem....:-

The UCC28070A datasheet shows nothing about disabling the UCC28070A by grounding its current error amp...

UCC28070A datasheet:-

not familiar with UCC28070A, however:

from the data sheet, pin 18, SS (soft start)
" Pulling the SS pin below 0.6 V immediately disables both GDA and GDB outputs."

i expect that turning off the gate drives will turn off the output.
Pulling those pins low will disable those channels - if you look at the history of these chips the error amps are designed to be over-ridden by such a pull down - as their outputs are limited to ~ 100uA - so there is no power dissipation issue.

In this case it appears the app note is in error and the line should go to the soft start pin.
Thanks, on the UCC28070A subject, it suffers an unfortunate primary leakage inductor of its CST in the drain. As such, the circuit as in Fig 19, Page 11 (of L4891A datasheet) is needed to freewheel this "inductor" current (D5, D6, D7, C14, R18).
Do you know why none of the (large number of) UCC28070A app notes even mentions need for a snubber, let alone this needed circuit?

I've just blown my UCC28070A board up due almost certainly to the overvoltage of this going to do some snubber surgery to PCB.

L4981A datasheet, Fig 19, page 11

There is no CST ( actually called a CT ) on page 11.

the current is sensed by the R in the gnd line, using a SiC diode will remove the need for snubbers - although a small one across both mosfet and diode is a good idea.
There is no CST ( actually called a CT ) on page 11.
Respectively I don't understand how the leakage inductance, snubber and board destroying discussion is related to the UCC28070A thread.
As for the original shut down question, I notice that the application example is only disabling one of the two channels which can't be achieved with SS pin. I guess they do intentionally.
The datasheet section 7.3.13 specifically addresses how to disable the chip by pulling down SS or Vsense. Years ago when I used the UCC28070, I pulled down SS to disable it. It was for a 20kW design, so we used LEM current sensors inline with the boost inductors instead of CTs on the FET drains (and thus we did not make use of the UCC28070's current ramp synthesizer feature).

Overriding the error amplifier outputs is an effective way of throttling the output power (for example, overriding VAO gives you direct control of output power), but I don't think it will totally disable the GDx outputs. You may still see narrow pulses coming out.
Shorting CAOx is how the device is internally disabled, e.g. by SS input. Review datasheet.

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