How to show a full adder output on a 7 segment display

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Hello,

I am a senior at Indiana State University. My major is Information Technology but I am taking a verilog class to get an intro into it. I created a full adder but I am not sure how to get it to display on a 7 segment display. I tried to do some research but the way some of the coding is confuses me.

This is what I have so far for my full adder that currently adds 3 inputs and produces a 4-bit output. 

Code Verilog - [expand]
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module Fulladd(
    input a,
    input b,
    input cin,
    output s,
    output cout
    );
    
    xor(s, a, b, cin);
    and(t1, a, b);
    and(t2, a, cin);
    and(t3, b, cin);
    or(cout, t1, t2, t3);
    
endmodule
 
module add3(a2, a1, a0, b2, b1, b0, s2, s1, s0, cout);
input a2, a1, a0, b2, b1, b0;
output cout, s2, s1, s0;
 
 
Fulladd stage0 (a0, b0, 0, s0, c1);
Fulladd stage1 (a1, b1, c1, s1, c2);
Fulladd stage2 (a2, b2, c2, s2, cout);
 

You need a 4-bit-to-seven-segment converter. This will map the sixteen 4-bit codes to enable the appropriate segments. For example, you can define the 7-segment display in a 7-bit register (segment A=bit 0, segment B=bit 1, etc.)

Code Enabled segments
0000 A,B,C,D,E,F-->0111111
0001 B,C-->0000110
0010 A,B,D,E,G
etc.

Code: 
--A---
|     |
F     B
|     |
---G---
|     |
E    C
|     |
--D---
Note: for some reason, this website strips away whitespaces. That's supposed to be a 7-seg display above.
 

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