Use a linear or stair case ramp of about 1bit/sample, and compare the converter's output to its input (reconvert the output by an ideal anti-converter, if necessary). You must take care of the time latency, apparently, (either in time or in voltage/bit domain).
For INL/DNL calculation, use their standard definitions, respectively.
Use a linear or stair case ramp of about 1bit/sample, and compare the converter's output to its input (reconvert the output by an ideal anti-converter, if necessary). You must take care of the time latency, apparently, (either in time or in voltage/bit domain).
For INL/DNL calculation, use their standard definitions, respectively.
Sure, this is also a very valuable method, however needs more effort in simulation and data processing. S. e.g. p.3 (Fig. 8 ) of the PDF below. Fig. 10 on p. 4 shows the standard DNL / INL presentations.