how to sequence ipcore?

[Indrajit Ghosh]

what I want to achieve is that

I have two cores p1 and p2 whose instantiation template is as

sub p1 (.output(Y),.a(A),.b(B),.clk(clk));

add p2 (.output(Z),.a(Y),.b(C),.clk(clk));

now as you can see the second core uses the output signal of the first core.....now when core p1 evaluates it should take
some clock cycles to complete its execution right? since the two instantiation will work simultaneously ,wouldn't the intermediates
results of core p2 will be erroneous? The final result would be correct but what about the intermediate result?...Now to make the core 2 wait for the result of core 1 to finish will i have to use handshaking signals?

 

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now as you can see the second core uses the output signal of the first core.....now when core p1 evaluates it should take some clock cycles to complete its execution right? since the two instantiation will work simultaneously ,wouldn't the intermediates results of core p2 will be erroneous? The final result would be correct but what about the intermediate result?...Now to make the core 2 wait for the result of core 1 to finish will i have to use handshaking signals?

That is what is called pipeline latency. You only get good data after the pipeline is filled.

If you need to know when the data output is valid then generate a valid signal along with each input data that propagates with the same latency as the pipeline. As long as you have valid input data the valid stays active and that valid will propagate down the pipeline that matches the latency of each instance.

 

[Indrajit Ghosh]

if suppose the ready signal of an ipcore goes high after a valid result ,and if i want to make the ipcore evaluate multiple times will i have to clear the ready signal using the sclr (synchronous clear) control signal or will it be cleared automatically when new operands will be evaluated?

Since i am using the ready signal as to enable other instantiations,I am using floating point ip core.

 

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if suppose the ready signal of an ipcore goes high after a valid result ,and if i want to make the ipcore evaluate multiple times will i have to clear the ready signal using the sclr (synchronous clear) control signal or will it be cleared automatically when new operands will be evaluated?

Since i am using the ready signal as to enable other instantiations,I am using floating point ip core.

Is the core pipelined or not? If it's pipelined then it will output valid data after a given pipeline latency until you stop inputting valid data.

If the core has a request/acknowledge interface then you'll have to adhere to the interface protocol.

As you posted some generic piece of code with a non-specific question I gave ONE answer out of many that could be given.

If you want an answer that is specific to your application then provide the entire code you are working with.

 

[Indrajit Ghosh]

Is the core pipelined or not? If it's pipelined then it will output valid data after a given pipeline latency until you stop inputting valid data.

If the core has a request/acknowledge interface then you'll have to adhere to the interface protocol.

As you posted some generic piece of code with a non-specific question I gave ONE answer out of many that could be given.

If you want an answer that is specific to your application then provide the entire code you are working with.

The ip core i am working with is this one....


https://www.xilinx.com/support/documentation/ip_documentation/floating_point_ds335.pdf

 

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At this point all I can assume is you haven't read the document or you don't understand the document.

All of the pipelining details, latency tradeoffs, and the significance of the RDY, OPERATION_ND, and OPERATION_RDY are specified in the documentation. You can configure the core to be fully pipelined, partially pipelined, etc. So I don't know what you did in your specification of the core, since I don't have a magic crystal ball.

If there are specific things in the document that you don't understand it might be better to ask questions about that instead of a generic question about how do I hook up two cores to do some sequential calculation.